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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1992 mos integrated circuit m m m m pd43257b 256k-bit cmos static ram 32k-word by 8-bit data sheet document no. m10693ej7v0ds00 (7th edition) date published june 2000 ns cp (k) printed in japan the mark h shows major revised points. description the m pd43257b is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) cmos static ram. battery backup is available. and the m pd43257b has two chip enable pins (/ce1, ce2) to extend the capacity. the m pd43257b is packed in 28-pin plastic dip and 28-pin plastic sop. features 32,768 words by 8 bits organization fast access time: 70, 85 ns (max.) low v cc data retention: 2.0 v (min.) two chip enable inputs: /ce1, ce2 part number access time operating supply operating ambient supply current ns (max.) voltage temperature at operating at standby at data retention v c ma (max.) m a (max.) m a (max.) note m pd43257b-xxl 70, 85 4.5 to 5.5 0 to 70 45 50 3 m pd43257b-xxll 45 15 2 note t a 40 c, v cc = 3.0 v version x this data sheet can be applied to the version x. this version is identified with its lot number. letter x in the fifth character position in a lot number signifies version x. x d43257b lot number japan
data sheet m10693ej7v0ds00 2 m m m m pd43257b ordering information part number package access time supply current m a (max.) remark ns (max.) at standby at data retention note m pd43257bcz-70l 28-pin plastic dip 70 50 3 l version m pd43257bcz-85l (15.24 mm (600)) 85 m pd43257bcz-70ll 70 15 2 ll version m pd43257bcz-85ll 85 m pd43257bgu-70l 28-pin plastic sop 70 50 3 l version m pd43257bgu-85l (11.43 mm (450)) 85 m pd43257bgu-70ll 70 15 2 ll version m pd43257bgu-85ll 85 note t a 40 c, v cc = 3.0 v
data sheet m10693ej7v0ds00 3 m m m m pd43257b pin configurations (marking side) /xxx indicates active low signal. 28-pin plastic dip (15.24 mm (600)) [ m m m m pd43257bcz-xxl ] [ m m m m pd43257bcz-xxll ] a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd v cc /we a13 a8 a9 a11 ce2 a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a0 - a14 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1 : chip enable 1 ce2 : chip enable 2 /we : write enable v cc : power supply gnd : ground remark refer to package drawings for the 1-pin marking.
data sheet m10693ej7v0ds00 4 m m m m pd43257b 28-pin plastic sop (11.43 mm (450)) [ m m m m pd43257bgu-xxl ] [ m m m m pd43257bgu-xxll ] a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd v cc /we a13 a8 a9 a11 ce2 a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a0 - a14 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1 : chip enable 1 ce2 : chip enable 2 /we : write enable v cc : power supply gnd : ground remark refer to package drawings for the 1-pin marking.
data sheet m10693ej7v0ds00 5 m m m m pd43257b block diagram address buffer memory cell array 262,144 bits input data controller a0 a14 i/o8 sense amplifier / switching circuit column decoder /ce1 /we ce2 output data controller i/o1 v cc gnd address buffer row decoder truth table /ce1 ce2 /we mode i/o supply current h not selected high impedance i sb l l h h read d out i cca lhl write d in remark : v ih or v il
data sheet m10693ej7v0ds00 6 m m m m pd43257b electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc C0.5 note to +7.0 v input / output voltage v t C0.5 note to v cc + 0.5 v operating ambient temperature t a 0 to 70 c storage temperature t stg C55 to +125 c note C3.0 v (min.) (pulse width : 50 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v high level input voltage v ih 2.2 v cc +0.5 v low level input voltage v il C0.3 note +0.8 v operating ambient temperature t a 070 c note C3.0 v (min.) (pulse width: 50 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test conditions min. typ. max. unit input capacitance c in v in = 0 v 5 pf input / output capacitance c i/o v i/o = 0 v 8 pf remarks 1. v in : input voltage v i/o : input / output voltage 2. these parameters are periodically sampled and not 100% tested.
data sheet m10693ej7v0ds00 7 m m m m pd43257b dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition m pd43257b-xxl m pd43257b-xxll unit min. typ. max. min. typ. max. input leakage i li v in = 0 v to v cc C1.0 +1.0 C1.0 +1.0 m a current i/o leakage i lo v i/o = 0 v to v cc , /ce1 = v ih or C1.0 +1.0 C1.0 +1.0 m a current ce2 = v il or /we = v il operating i cca1 /ce1 = v il , ce2 = v ih , m pd43257b-70 45 45 ma supply current minimum cycle time, i i/o = 0 ma m pd43257b-85 45 45 i cca2 /ce1 = v il , ce2 = v ih , i i/o = 0 ma 10 10 i cca3 /ce1 0.2 v, ce2 3 v cc C 0.2 v, cycle = 1 mhz, 10 10 i i/o = 0 ma, v il 0.2 v, v ih 3 v cc C 0.2 v standby i sb /ce1 = v ih or ce2 = v il ,33ma supply current i sb1 /ce1 3 v cc - 0.2 v, ce2 3 v cc - 0.2 v 1.0 50 0.5 15 m a i sb2 ce2 0.2 v 1.0 50 0.5 15 high level v oh1 i oh = C1.0 ma 2.4 2.4 v output voltage v oh2 i oh = C0.1 ma v cc C0.5 v cc C0.5 low level v ol i ol = 2.1 ma 0.4 0.4 v output voltage remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of package types and access time.
data sheet m10693ej7v0ds00 8 m m m m pd43257b ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions [ m m m m pd43257b-70l, m m m m pd43257b-85l, m m m m pd43257b-70ll, m m m m pd43257b-85ll ] input waveform (rise and fall time 5 ns) test points 0.8 v 2.2 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load ac characteristics with notes should be measured with the output load shown in figure 1 and figure 2 . figure 1 figure 2 (t aa , t co1 , t co2 , t oh ) (t lz1 , t lz2 , t hz1 , t hz2 , t whz , t ow ) +5 v i/o (output) 1.8 k w 5 pf c l 990 w +5 v i/o (output) 1.8 k w 100 pf c l 990 w remark c l includes capacitance of the probe and jig, and stray capacitance.
data sheet m10693ej7v0ds00 9 m m m m pd43257b read cycle parameter symbol m pd43257b-70 m pd43257b-85 unit condition min. max. min. max. read cycle time t rc 70 85 ns address access time t aa 70 85 ns note 1 /ce1 access time t co1 70 85 ns ce2 access time t co2 70 85 ns output hold from address change t oh 10 10 ns /ce1 to output in low impedance t lz1 10 10 ns note 2 ce2 to output in low impedance t lz2 10 10 ns /ce1 to output in high impedance t hz1 30 30 ns ce2 to output in high impedance t hz2 30 30 ns notes 1. see the output load shown in figure 1 . 2. see the output load shown in figure 2 . remark these ac characteristics are in common regardless of package types and l, ll versions. read cycle timing chart t hz2 t rc t oh t hz1 t lz2 t co2 t lz1 t co1 t aa high impedance data out ce2 (input) /ce1 (input) address (input) i/o (output) remark in read cycle, /we should be fixed to high level.
data sheet m10693ej7v0ds00 10 m m m m pd43257b write cycle parameter symbol m pd43257b-70 m pd43257b-85 unit condition min. max. min. max. write cycle time t wc 70 85 ns /ce1 to end of write t cw1 50 70 ns ce2 to end of write t cw2 50 70 ns address valid to end of write t aw 50 70 ns address setup time t as 00ns write pulse width t wp 55 65 ns write recovery time t wr 00ns data valid to end of write t dw 30 35 ns data hold time t dh 00ns /we to output in high impedance t whz 30 30 ns note output active from end of write t ow 10 10 ns note see the output load shown in figure 2 . remark these ac characteristics are in common regardless of package types and l, ll versions.
data sheet m10693ej7v0ds00 11 m m m m pd43257b write cycle timing chart 1 (/we controlled) t wc t cw1 t whz t dw t dh t ow indefinite data out high impe- dance high impe- dance data in indefinite data out address (input) /ce1 (input) i/o (input / output) ce2 (input) t cw2 t aw t wp t as t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, therefore the input signals must not be applied to the output. remarks 1. write operation is done during the overlap time of a low level /ce1, /we and a high level ce2. 2. if /ce1 changes to low level at the same time or after the change of /we to low level, or if ce2 changes to high level at the same time or after the change of /we to low level, the i/o pins will remain high impedance state. 3. when /we is at low level, the i/o pins are always high impedance. when /we is at high level, read operation is executed. therefore /oe should be at high level to make the i/o pins high impedance. h
data sheet m10693ej7v0ds00 12 m m m m pd43257b write cycle timing chart 2 (/ce1 controlled) t wc t as t cw1 t dw t dh data in high impedance address (input) /ce1 (input) i/o (input) high impedance ce2 (input) t cw2 t aw t wp t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, therefore the input signals must not be applied to the output. remark write operation is done during the overlap time of a low level /ce1, /we and a high level ce2. h
data sheet m10693ej7v0ds00 13 m m m m pd43257b write cycle timing chart 3 (ce2 controlled) t wc t as t cw2 t dw t dh data in high impedance address (input) ce2 (input) i/o (input) high impedance /ce1 (input) t cw1 t aw t wp t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, therefore the input signals must not be applied to the output. remark write operation is done during the overlap time of a low level /ce1, /we and a high level ce2. h
data sheet m10693ej7v0ds00 14 m m m m pd43257b low v cc data retention characteristics (t a = 0 to 70 c) parameter symbol test condition m pd43257b-xxl m pd43257b-xxll unit min. typ. max. min. typ. max. data retention supply voltage v ccdr1 /ce1 3 v cc - 0.2 v, ce2 3 v cc - 0.2 v 2.0 5.5 2.0 5.5 v v ccdr2 ce2 0.2 v 2.0 5.5 2.0 5.5 data retention supply current i ccdr1 v cc = 3.0 v, /ce1 3 v cc - 0.2 v, ce2 3 v cc - 0.2 v 0.5 20 note1 0.5 7 note2 m a i ccdr2 v cc = 3.0 v, ce2 0.2 v 0.5 20 note1 0.5 7 note2 chip deselection to data retention mode t cdr 00ns operation recovery time t r 55ms notes 1. 3 m a (t a 40 c) 2. 2 m a (t a 40 c), 1 m a (t a 25 c)
data sheet m10693ej7v0ds00 15 m m m m pd43257b data retention timing chart (1) /ce1 controlled v ih (min.) v ccdr (min.) v il (max.) v cc /ce1 /ce1 3 v cc C 0.2 v gnd 4.5 v t cdr data retention mode t r remark on the data retention mode by controlling /ce1, the input level of ce2 must be ce2 3 v cc - 0.2 v or ce2 0.2 v. the other pins (address, i/o, /we) can be in high impedance state. (2) ce2 controlled v ih (min.) v ccdr (min.) v il (max.) v cc ce2 ce2 0.2 v gnd 4.5 v t cdr data retention mode t r remark on the data retention mode by controlling ce2, the other pins (/ce1, address, i/o, /we) can be in high impedance state. h h
data sheet m10693ej7v0ds00 16 m m m m pd43257b package drawings item millimeters a b c f g h i j k 38.10 max. 2.54 (t.p.) 3.6 0.3 0.51 min. 4.31 max. 2.54 max. l 0.25 15.24 (t.p.) 5.72 max. 13.2 n 1.2 min. p28c-100-600a1-2 d 0.50 0.10 m 0.25 + 0.10 - 0.05 r0 ~ 15 notes each lead centerline is located within 0.25 mm of its true position (t.p.) at maximum material condition. item "k" to center of leads when formed parallel. 1. 2. 28 1 15 14 a m r k l b j g i c f d m n 28-pin plastic dip (15.24 mm (600)) h h
data sheet m10693ej7v0ds00 17 m m m m pd43257b 28 15 114 s - 3 item millimeters a b c e f g h j 18.0 1.27 (t.p.) 2.95 max. 2.55 0.1 11.8 0.3 1.27 max. 0.12 1.7 0.2 m 0.2 0.1 n p28gu-50-450a-4 p3 + 7 note each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. d 0.42 + 0.08 - 0.07 k 0.22 0.05 + 0.6 - 0.05 l 0.7 0.2 0.10 i 8.4 0.1 28-pin plastic sop (11.43 mm (450)) m f e dm c g b l j k p detail of lead end a s n i h
data sheet m10693ej7v0ds00 18 m m m m pd43257b recommended soldering conditions the following conditions must be met when soldering m pd43257b. for more details, refer to our document semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. types of surface mount device m pd43257bgu-xxl : 28-pin plastic sop (11.43 mm (450)) m pd43257bgu-xxll : 28-pin plastic sop (11.43 mm (450)) please consult with our sales offices. types of through hole mount device m pd43257bcz-xxl : 28-pin plastic dip (15.24 mm (600)) m pd43257bcz-xxll : 28-pin plastic dip (15.24 mm (600)) soldering process soldering conditions wave soldering (only to leads) solder temperature : 260 c or below, flow time : 10 seconds or below partial heating method terminal temperature : 300 c or below, time : 3 seconds or below (per one lead) caution do not jet molten solder on the surface of package.
data sheet m10693ej7v0ds00 19 m m m m pd43257b notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd43257b m8e 00. 4 the information in this document is current as of june, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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